Commit 80a7a124 authored by Daniel Toyra's avatar Daniel Toyra
Browse files

Commented out a line in the fsig parsing

parent 0a39c61a
......@@ -1015,7 +1015,7 @@ class kat(object):
amp = None
if len(v) == 5:
param is None
#param is None
freq = SIfloat(v[3])
phase = SIfloat(v[4])
elif len(v) == 6:
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